A memory block of a memory device, such as a NOT AND (NAND) or NOT OR (NOR) memory, may comprise a group of strings of memory cells that share the same set of access lines. The memory block may be grouped into a plurality of pages, and each page may comprise all or a subset of the memory cells corresponding to at least a portion of a respective tier of each of the group of strings, for example, depending on whether the memory cells are single-level cells (SLCs) or multi-level cells (MLCs).
Under existing semiconductor memory techniques, a memory operation may be performed on an entire memory block (e.g., if the memory operation is an erase), or on an entire (selected) page within the memory block (e.g., if the memory operation is a program, read or verify). Accordingly, as the page size becomes larger, the power used during a data line swing or page buffer flip may increase, so that a relatively large amount of power may be consumed when relatively small amounts of data, such as four (4) Kilo Bytes (KBs), are read, programmed, erased or verified. This tendency may be enhanced when an ABL (all-bit line) architecture is used, in comparison with a SBL (shielded bit line) architecture. Thus, as the size of the (single) memory block or page increases, as in the case of three-dimensional (3D) memory devices, so does the current consumption or parasitic current leakage when memory operations are performed, because the number of memory cells in the memory block or page on which the memory operations are performed concurrently also increases. This may result in the need to supply the memory device with additional or alternative power sources to support the extensive current consumption or parasitic leakage.
In addition, a host that operably communicates with a memory device formed according to existing technologies, for example, via a memory controller, may process data in a smaller unit than a page size of the memory device. Thus, conventional memory devices may require all of the page data to be filled in a page buffer before programming.
For example, when the memory device comprises a NAND memory, the host may process data in four (4) Kilo Bytes (KBs) units while the page size of the NAND memory is sixteen (16) KBs. In this case, the host may transmit or receive data to or from the memory controller controlling the NAND memory in four (4) KB s units via a page buffer while the memory controller transmits or receives the data to or from the NAND memory in sixteen (16) KBs units. Thus, the memory controller may need to wait and pack the data received from the host until the total size of the (received) data becomes sixteen (16) KBs before programming it to the NAND memory. If some portions of the relevant page are not filled, then the unfilled portions cannot be programmed at a later time without first having to erase the entire block to remove all of the data programmed in the block. This may result in undesired performance, such as a slower programming speed and a higher current consumption or parasitic current leakage, as described above, and so on.